1. Field of the Invention
This invention relates to a electrostatic protection circuit for protecting against both positive and negative pulses of static electricity, and more particularly, to an electrostatic protection circuit for protecting against static electricity which may be applied from any source, including power supply terminals, by constructing respective protection circuits for each power supply terminal so that an internal circuit can be protected from the static electricity flowing thereto through bonding pads.
2. Description of the Related Art
In conventional complementary metal oxide semiconductor (CMOS) analog circuits, the substrate bias or voltage and the source bias or voltage of the transistor are isolated from each other in an effort to reduce noise, as shown in the input buffer (or load) and an output driver circuits in FIGS. 1A and 1B, respectively.
The CMOS analog circuits operate in the following manner when a pulse of static electricity is applied through bonding pads 1 and 2.
First, when a reference power supply terminal Vdd is grounded and a positive pulse is applied to the bonding pads 1 and 2, the region between a p.sup.+ -type drain of the PMOS transistor T1 and an n.sup.- -type well is forward-biased, and thus exhibits good electrostatic protection, assuming the transistor T1 has sufficient discharging capacity.
When a negative pulse is applied to the bonding pads 1 and 2, the static electricity will be discharged through either a pnp-type bipolar junction transistor (BJT), formed between source and drain regions and an n.sup.- -type well region of the PMOS transistor T1, or a protective element formed between a reference power supply terminal Vdd and an NMOS transistor T2 coupled to a reference ground terminal Vss. The particular discharge path is determined by the level of the operating voltage of the BJT and the protective element.
Second, when the source bias or reference ground terminal Vss of the NMOS transistor T2 is grounded and a negative pulse is applied to the bonding pads 1 and 2, the degree of electrostatic protection is proportional to the size of transistor T2 since the substrate is biased by the substrate voltage Vbb. The PMOS transistor T1 does not operate as a diode coupled between an n.sup.+ -type drain and a p.sup.- -type substrate, causing the transistor T2 to function as a npn-type BJT.
When a positive pulse is applied to the bonding pads 1 and 2, there is excellent electrostatic protection since the npn-type BJT operates at its breakdown voltage BVceo state, i.e., in an open-circuit state.
Third, when the substrate voltage Vbb is grounded and a negative pulse of static electricity is applied to the bonding pads 1 and 2, there is excellent electrostatic protection since the n.sup.+ /p.sup.- type diode formed between an n.sup.30 -type drain and a p.sup.- - type substrate region operates in a forward-biased state.
When a positive pulse is applied to the bonding pads 1 and 2, a parasitic BJT is not formed because the source of the transistor, which is an emitter region of the parasitic BJT, is open-circuited. Thus, electrostatic protection deteriorates since the static electricity is discharged by the n.sup.+ /p.sup.- diode feature (see FIG. 3) without utilization of the snap-back phenomenon, which is the major operational mechanism for discharging the static electricity (see FIG. 2).
FIGS. 4A and 4B illustrate conventional electrostatic protection circuits provided in the respective input driver and output buffer circuits. In FIGS. 4A and 4B, the PMOS transistor T1 acts as the input buffer, while the NMOS transistor T2 acts as the output driver. Each pair of NMOS transistors T3, T4 and T5, T6, which are connected to the input buffer and the output driver, respectively, represent protective elements for protecting the internal circuit against static electricity applied from a voltage source of the circuit.
The NMOS transistors T3 and T5 act as the electrostatic protection circuits for the reference power supply terminal Vdd. Transistors T3 and T5 have their respective sources connected to the reference power supply terminal Vdd, their respective drains to the bonding pads 1 and 2, and their respective gates to the reference ground terminal Vss. The substrate is biased by the substrate voltage Vbb.
The NMOS transistors T4 and T6 act as the electrostatic protection circuits for the reference ground terminal Vss. Transistors T4 and T6 have their respective sources connected to the reference ground terminal Vss, their respective drains to the bonding pads 1 and 2, and their respective gates to the reference ground terminal Vss. The substrate is biased by the substrate voltage Vbb.
The operation of these conventional electrostatic protection circuits will now be described. When the source biases comprising the reference ground terminal Vss and the substrate voltage Vbb are grounded, the static electricity will be discharged in the same manner as described in the second and third situations above.
When the reference power supply terminal Vdd is grounded and a negative pulse is applied, the NMOS transistors T3 and T5 discharge the static electricity by the operation of the parasitic BJT. If a positive pulse is applied, the NMOS transistors T3 and T5 operate at the breakdown voltage BVceo. The PMOS transistor T1 forms a p.sup.+ /n.sup.- -type diode between the drain and the n-type well thereof, and thus discharges the overflow current caused by the static electricity at a lower voltage than in the NMOS transistor T2.
Thus, excellent electrostatic protection can be obtained under the condition that the size of the PMOS transistor is large enough to discharge the overflow current applied thereto. If, however, the PMOS transistor is too small, several problems may occur.
Therefore, the conventional electrostatic protection circuits shown in FIGS. 4A and 4B are limited to use in those situations where the PMOS transistor is large enough to satisfy the electrostatic discharge (ESD) standards.